For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity.
Recently, research on III-V devices like high electron mobility transistors (HEMT) employing quantum-well field effect transistors (QWFET) has increased. Quantum-well devices are typically formed in epitaxially grown semiconductor hetero-structures, such as in compound semiconductor materials like III-V systems. Such devices offer the promise of exceptionally high carrier mobility in the transistor channels due to low effective carrier mass.
However, the electrically poor quality native oxide (e.g., in contrast to SiO2 for silicon-based devices) formed by compound semiconductor materials has hindered widespread adoption of III-V semiconductor transistor devices. While some have proposed growing a high-K material in-situ with the formation of an underlying semiconductor layer, such procedures require an expensive molecular beam epitaxy (MBE) technique and also high temperatures (e.g., 600° C.) which preclude the use of certain semiconductor materials which have low decomposition temperatures (e.g., InP) and are also not compatible with “gate-last” processing in which a gate stack is formed after formation and anneal of source/drain regions of the QWFET device.